In addition to my session on Move Semantics, Rvalue References, and Perfect Forwarding, I’ll be giving a session on CPU caches and why they are important for people interested in developing performance-sensitive software.  Topics I’ll be discussing include:

  • Instruction caches vs. data caches vs. TLBs.
  • Cache lines, cache line prefetching, and false sharing.
  • Cache hierarchies.
  • Shared and unshared caches.
  • Cache associativity and counterintuitive cache behavior.

Cache behavior is both important and interesting, so I think this session will be a lot of fun.  If you have suggestions on information I should include in this session, let me know via comment on this blog entry or via email (smeyers@aristeia.com).

Thanks,

Scott